1. Field of the Invention
This invention is related to a structure and method for fully testing integrated circuit chips before they are incorporated into high density interconnect (HDI) circuits or other standard bare chip hybrid circuits and, more particularly, to a structure and method for testing and burning-in one or more integrated circuit chips positioned in a pin grid array or other substrate structure, using conventional techniques, prior to incorporating them into the HDI or standard bare chip hybrid circuitry.
2. Description of the Prior Art
HDI circuits are comprised of a plurality of integrated circuit chips mounted on a substrate, the chips being interconnected by a metallization pattern created on a polymer overlay layer. In some HDI circuits, a multilayer interconnect pattern comprised of a plurality of polymer overlay layers is formed over the chips, each layer having its own interconnect pattern formed thereon. Typically, the interconnect pattern is formed by computer controlled laser lithography. The above-referenced co-pending patent applications describe and illustrate these circuits in great detail.
Heretofore, testing very large scale integrated circuit (VLSI) chips or other high speed chips has been performed by probing at the wafer level only to a degree sufficient to gain some assurance that the chips are not defective, or bad. The chips found not to be defective are packaged and then tested with the full test vectors at "full speed" (i.e., rated frequency). The packaged chips are burned-in by a conventional bias method, as set forth in Mil Standard 883C dated Aug. 25, 1983, at Test Method 1015.4 entitled "Burn-in Test". The bias method of burn-in has been found to be the surest way to identify weak or marginal chips.
An important feature that distinguishes HDI circuits, as well as standard hybrid circuits, from conventional circuitry is that the chips employed in the circuit are not packaged, but instead remain bare in the circuit. The chips are interconnected by a metal interconnect pattern formed on a polymer overlay layer in the HDI circuitry, while the chips are nail-head bonded in place in standard hybrid circuitry. Commercially available testing and burn-in devices cannot be used to fully test or burn-in unpackaged chips to be used in HDI circuits or other bare chip circuit designs. This is so because probing devices are limited to a relatively low megahertz (MHZ) region and have high capacitance loading. As a result, the chips are not completely tested, so that weak and marginal chips can be incorporated into an HDI circuit and hinder its functionality. This lack of adequate pretesting results in low yield and costly rework procedures.
A major difficulty in testing integrated circuit chips used in HDI circuits stems from the fact that the chips often have a large number of interconnect pads and that the interconnect pads are too small to be probed by conventional wafer probing equipment. Because the HDI chip interconnection method eliminates the chip package, the number of interconnects on a chip can be increased substantially and the size of the interconnect pads can be decreased drastically. In the past, the number and size of interconnect pads has not posed a problem because the size of the package limited those parameters to readily workable values.